14. Coprocessor 0
The Count register acts as a real-time timer. Like the R4400 implementation, the R10000 Count register is incremented every other PClk cycle. However, unlike the R4400, the R10000 processor has no Timer Interrupt Enable boot-mode bit, so the only way to disable the timer interrupt is to negate the interrupt mask bit, IM[7], in the Status register. This means the timer interrupt cannot be disabled without also disabling the Performance Counter interrupt, since they share IM[7].
The Compare register can be programmed to generate an interrupt at a particular time, and is continually compared to the Count register. Whenever their values equal, the interrupt bit IP[7] in the Cause register is set. This interrupt bit is reset whenever the Compare register is written.
Figure 14-9 Count and Compare Registers
